In general, semiconductor devices are manufactured by fabrication processes that form electric circuits on a semiconductor substrate, such as a silicon wafer. Metals, like copper, are commonly deposited on the substrate to form the electric circuits. It is well known, however, that copper ions act as a contaminant in semiconductor fabrication. For example, copper ions will diffuse into a silicon substrate and change the conductivity of the silicon. Therefore, a barrier metal layer must completely surround all copper interconnections to prevent the diffusion of copper ions into the surrounding materials. A seed layer is subsequently deposited on the barrier layer to facilitate copper interconnect plating.
Recently, ruthenium has been introduced as a seed layer material to replace commonly used copper seed layers. One drawback of using ruthenium as a seed layer is that it tends to oxidize quickly. The native oxide layer that forms is not an optimal surface for copper plating, particularly for small-sized damascene fill features (such as vias and trenches), for example, features measuring less than 40 nm in width. Therefore, the oxide layer must be reduced prior to initiating copper plating processes. Once reduced, however, oxides will quickly form again.
Therefore, there exists a need for an improved process for passivating a seed layer after oxide reduction to slow the re-oxidation process of the metal seed layer and to enhance metal deposition. There also exists a need for a device for passivating a workpiece and/or containing a workpiece having a passivated seed layer.